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tn_arch_pic32.h
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1 /*******************************************************************************
2  *
3  * TNeo: real-time kernel initially based on TNKernel
4  *
5  * TNKernel: copyright © 2004, 2013 Yuri Tiomkin.
6  * PIC32-specific routines: copyright © 2013, 2014 Anders Montonen.
7  * TNeo: copyright © 2014 Dmitry Frank.
8  *
9  * TNeo was born as a thorough review and re-implementation of
10  * TNKernel. The new kernel has well-formed code, inherited bugs are fixed
11  * as well as new features being added, and it is tested carefully with
12  * unit-tests.
13  *
14  * API is changed somewhat, so it's not 100% compatible with TNKernel,
15  * hence the new name: TNeo.
16  *
17  * Permission to use, copy, modify, and distribute this software in source
18  * and binary forms and its documentation for any purpose and without fee
19  * is hereby granted, provided that the above copyright notice appear
20  * in all copies and that both that copyright notice and this permission
21  * notice appear in supporting documentation.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE DMITRY FRANK AND CONTRIBUTORS "AS IS"
24  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DMITRY FRANK OR CONTRIBUTORS BE
27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33  * THE POSSIBILITY OF SUCH DAMAGE.
34  *
35  ******************************************************************************/
36 
37 /**
38  *
39  * \file
40  *
41  * PIC32 architecture-dependent routines
42  *
43  */
44 
45 #ifndef _TN_ARCH_PIC32_H
46 #define _TN_ARCH_PIC32_H
47 
48 
49 /*******************************************************************************
50  * INCLUDED FILES
51  ******************************************************************************/
52 
53 #include "../../core/tn_cfg_dispatch.h"
54 
55 //-- include macros for atomic assess to structure bit fields so that
56 // application can use it too.
57 #include "tn_arch_pic32_bfa.h"
58 
59 
60 
61 #ifdef __cplusplus
62 extern "C" { /*}*/
63 #endif
64 
65 
66 /*******************************************************************************
67  * PROTECTED GLOBAL DATA
68  ******************************************************************************/
69 
70 /// current interrupt nesting count. Used by macros
71 /// `tn_p32_soft_isr()` and `tn_p32_srs_isr()`.
72 extern volatile int tn_p32_int_nest_count;
73 
74 /// saved task stack pointer. Needed when switching stack pointer from
75 /// task stack to interrupt stack.
76 extern void *tn_p32_user_sp;
77 
78 /// saved ISR stack pointer. Needed when switching stack pointer from
79 /// interrupt stack to task stack.
80 extern void *tn_p32_int_sp;
81 
82 
83 
84 
85 
86 
87 
88 
89 #ifndef DOXYGEN_SHOULD_SKIP_THIS
90 
91 #define _TN_PIC32_INTSAVE_DATA_INVALID 0xffffffff
92 
93 #if TN_DEBUG
94 # define _TN_PIC32_INTSAVE_CHECK() \
95 { \
96  if (tn_save_status_reg == _TN_PIC32_INTSAVE_DATA_INVALID){ \
97  _TN_FATAL_ERROR(""); \
98  } \
99 }
100 #else
101 # define _TN_PIC32_INTSAVE_CHECK() /* nothing */
102 #endif
103 
104 /**
105  * FFS - find first set bit. Used in `_find_next_task_to_run()` function.
106  * Say, for `0xa8` it should return `3`.
107  *
108  * May be not defined: in this case, naive algorithm will be used.
109  */
110 #define _TN_FFS(x) (32 - __builtin_clz((x) & (0 - (x))))
111 
112 /**
113  * Used by the kernel as a signal that something really bad happened.
114  * Indicates TNeo bugs as well as illegal kernel usage
115  * (e.g. sleeping in the idle task callback)
116  *
117  * Typically, set to assembler instruction that causes debugger to halt.
118  */
119 #define _TN_FATAL_ERROR(error_msg, ...) \
120  {__asm__ volatile(" sdbbp 0"); __asm__ volatile ("nop");}
121 
122 /**
123  * \def TN_ARCH_STK_ATTR_BEFORE
124  *
125  * Compiler-specific attribute that should be placed **before** declaration of
126  * array used for stack. It is needed because there are often additional
127  * restrictions applied to alignment of stack, so, to meet them, stack arrays
128  * need to be declared with these macros.
129  *
130  * @see TN_ARCH_STK_ATTR_AFTER
131  */
132 
133 /**
134  * \def TN_ARCH_STK_ATTR_AFTER
135  *
136  * Compiler-specific attribute that should be placed **after** declaration of
137  * array used for stack. It is needed because there are often additional
138  * restrictions applied to alignment of stack, so, to meet them, stack arrays
139  * need to be declared with these macros.
140  *
141  * @see TN_ARCH_STK_ATTR_BEFORE
142  */
143 
144 #if defined (__XC32)
145 # define TN_ARCH_STK_ATTR_BEFORE
146 # define TN_ARCH_STK_ATTR_AFTER __attribute__((aligned(0x8)))
147 #else
148 # error "Unknown compiler"
149 #endif
150 
151 /**
152  * Minimum task's stack size, in words, not in bytes; includes a space for
153  * context plus for parameters passed to task's body function.
154  */
155 #define TN_MIN_STACK_SIZE (36 + _TN_STACK_OVERFLOW_SIZE_ADD)
156 
157 /**
158  * Width of `int` type.
159  */
160 #define TN_INT_WIDTH 32
161 
162 /**
163  * Unsigned integer type whose size is equal to the size of CPU register.
164  * Typically it's plain `unsigned int`.
165  */
166 typedef unsigned int TN_UWord;
167 
168 /**
169  * Unsigned integer type that is able to store pointers.
170  * We need it because some platforms don't define `uintptr_t`.
171  * Typically it's `unsigned int`.
172  */
173 typedef unsigned int TN_UIntPtr;
174 
175 /**
176  * Maximum number of priorities available, this value usually matches
177  * `#TN_INT_WIDTH`.
178  *
179  * @see TN_PRIORITIES_CNT
180  */
181 #define TN_PRIORITIES_MAX_CNT TN_INT_WIDTH
182 
183 /**
184  * Value for infinite waiting, usually matches `ULONG_MAX`,
185  * because `#TN_TickCnt` is declared as `unsigned long`.
186  */
187 #define TN_WAIT_INFINITE (TN_TickCnt)0xFFFFFFFF
188 
189 /**
190  * Value for initializing the task's stack
191  */
192 #define TN_FILL_STACK_VAL 0xFEEDFACE
193 
194 
195 
196 
197 /**
198  * Declares variable that is used by macros `TN_INT_DIS_SAVE()` and
199  * `TN_INT_RESTORE()` for storing status register value.
200  *
201  * It is good idea to initially set it to some invalid value,
202  * and if TN_DEBUG is non-zero, check it in TN_INT_RESTORE().
203  * Then, we can catch bugs if someone tries to restore interrupts status
204  * without saving it first.
205  *
206  * @see `TN_INT_DIS_SAVE()`
207  * @see `TN_INT_RESTORE()`
208  */
209 #define TN_INTSAVE_DATA \
210  int tn_save_status_reg = _TN_PIC32_INTSAVE_DATA_INVALID;
211 
212 /**
213  * The same as `#TN_INTSAVE_DATA` but for using in ISR together with
214  * `TN_INT_IDIS_SAVE()`, `TN_INT_IRESTORE()`.
215  *
216  * @see `TN_INT_IDIS_SAVE()`
217  * @see `TN_INT_IRESTORE()`
218  */
219 #define TN_INTSAVE_DATA_INT TN_INTSAVE_DATA
220 
221 /**
222  * \def TN_INT_DIS_SAVE()
223  *
224  * Disable interrupts and return previous value of status register,
225  * atomically. Similar `tn_arch_sr_save_int_dis()`, but implemented
226  * as a macro, so it is potentially faster.
227  *
228  * Uses `#TN_INTSAVE_DATA` as a temporary storage.
229  *
230  * @see `#TN_INTSAVE_DATA`
231  * @see `tn_arch_sr_save_int_dis()`
232  */
233 
234 /**
235  * \def TN_INT_RESTORE()
236  *
237  * Restore previously saved status register.
238  * Similar to `tn_arch_sr_restore()`, but implemented as a macro,
239  * so it is potentially faster.
240  *
241  * Uses `#TN_INTSAVE_DATA` as a temporary storage.
242  *
243  * @see `#TN_INTSAVE_DATA`
244  * @see `tn_arch_sr_save_int_dis()`
245  */
246 
247 #ifdef __mips16
248 # define TN_INT_DIS_SAVE() tn_save_status_reg = tn_arch_sr_save_int_dis()
249 # define TN_INT_RESTORE() _TN_PIC32_INTSAVE_CHECK(); \
250  tn_arch_sr_restore(tn_save_status_reg)
251 #else
252 # define TN_INT_DIS_SAVE() __asm__ __volatile__( \
253  "di %0; ehb" \
254  : "=d" (tn_save_status_reg) \
255  )
256 # define TN_INT_RESTORE() _TN_PIC32_INTSAVE_CHECK(); \
257  __builtin_mtc0(12, 0, tn_save_status_reg)
258 #endif
259 
260 /**
261  * The same as `TN_INT_DIS_SAVE()` but for using in ISR.
262  *
263  * Uses `#TN_INTSAVE_DATA_INT` as a temporary storage.
264  *
265  * @see `#TN_INTSAVE_DATA_INT`
266  */
267 #define TN_INT_IDIS_SAVE() TN_INT_DIS_SAVE()
268 
269 /**
270  * The same as `TN_INT_RESTORE()` but for using in ISR.
271  *
272  * Uses `#TN_INTSAVE_DATA_INT` as a temporary storage.
273  *
274  * @see `#TN_INTSAVE_DATA_INT`
275  */
276 #define TN_INT_IRESTORE() TN_INT_RESTORE()
277 
278 /**
279  * Returns nonzero if interrupts are disabled, zero otherwise.
280  */
281 #define TN_IS_INT_DISABLED() ((__builtin_mfc0(12, 0) & 1) == 0)
282 
283 /**
284  * Pend context switch from interrupt.
285  */
286 #define _TN_CONTEXT_SWITCH_IPEND_IF_NEEDED() \
287  _tn_context_switch_pend_if_needed()
288 
289 /**
290  * Converts size in bytes to size in `#TN_UWord`.
291  * For 32-bit platforms, we should shift it by 2 bit to the right;
292  * for 16-bit platforms, we should shift it by 1 bit to the right.
293  */
294 #define _TN_SIZE_BYTES_TO_UWORDS(size_in_bytes) ((size_in_bytes) >> 2)
295 
296 #define _TN_INLINE inline
297 
298 #define _TN_VOLATILE_WORKAROUND /* nothing */
299 
300 #endif //-- DOXYGEN_SHOULD_SKIP_THIS
301 
302 
303 
304 
305 
306 
307 
308 
309 
310 
311 // ---------------------------------------------------------------------------
312 
313 /**
314  * Interrupt handler wrapper macro for software context saving.
315  *
316  * Usage looks like the following:
317  *
318  * tn_p32_soft_isr(_TIMER_1_VECTOR)
319  * {
320  * INTClearFlag(INT_T1);
321  *
322  * //-- do something useful
323  * }
324  *
325  * Note that you should not use `__ISR(_TIMER_1_VECTOR)` macro for that.
326  *
327  * @param vec interrupt vector number, such as `_TIMER_1_VECTOR`, etc.
328  */
329 #define tn_p32_soft_isr(vec) \
330 __attribute__((__noinline__)) void _func##vec(void); \
331 void __attribute__((naked, nomips16)) \
332  __attribute__((vector(vec))) \
333  _isr##vec(void) \
334 { \
335  asm volatile(".set push"); \
336  asm volatile(".set mips32r2"); \
337  asm volatile(".set nomips16"); \
338  asm volatile(".set noreorder"); \
339  asm volatile(".set noat"); \
340  \
341  asm volatile("rdpgpr $sp, $sp"); \
342  \
343  /* Increase interrupt nesting count */ \
344  asm volatile("lui $k0, %hi(tn_p32_int_nest_count)"); \
345  asm volatile("lw $k1, %lo(tn_p32_int_nest_count)($k0)"); \
346  asm volatile("addiu $k1, $k1, 1"); \
347  asm volatile("sw $k1, %lo(tn_p32_int_nest_count)($k0)"); \
348  asm volatile("ori $k0, $zero, 1"); \
349  asm volatile("bne $k1, $k0, 1f"); \
350  \
351  /* Swap stack pointers if nesting count is one */ \
352  asm volatile("lui $k0, %hi(tn_p32_user_sp)"); \
353  asm volatile("sw $sp, %lo(tn_p32_user_sp)($k0)"); \
354  asm volatile("lui $k0, %hi(tn_p32_int_sp)"); \
355  asm volatile("lw $sp, %lo(tn_p32_int_sp)($k0)"); \
356  \
357  asm volatile("1:"); \
358  /* Save context on stack */ \
359  asm volatile("addiu $sp, $sp, -92"); \
360  asm volatile("mfc0 $k1, $14"); /* c0_epc*/ \
361  asm volatile("mfc0 $k0, $12, 2"); /* c0_srsctl*/ \
362  asm volatile("sw $k1, 84($sp)"); \
363  asm volatile("sw $k0, 80($sp)"); \
364  asm volatile("mfc0 $k1, $12"); /* c0_status*/ \
365  asm volatile("sw $k1, 88($sp)"); \
366  \
367  /* Enable nested interrupts */ \
368  asm volatile("mfc0 $k0, $13"); /* c0_cause*/ \
369  asm volatile("ins $k1, $zero, 1, 15"); \
370  asm volatile("ext $k0, $k0, 10, 6"); \
371  asm volatile("ins $k1, $k0, 10, 6"); \
372  asm volatile("mtc0 $k1, $12"); /* c0_status*/ \
373  \
374  /* Save caller-save registers on stack */ \
375  asm volatile("sw $ra, 76($sp)"); \
376  asm volatile("sw $t9, 72($sp)"); \
377  asm volatile("sw $t8, 68($sp)"); \
378  asm volatile("sw $t7, 64($sp)"); \
379  asm volatile("sw $t6, 60($sp)"); \
380  asm volatile("sw $t5, 56($sp)"); \
381  asm volatile("sw $t4, 52($sp)"); \
382  asm volatile("sw $t3, 48($sp)"); \
383  asm volatile("sw $t2, 44($sp)"); \
384  asm volatile("sw $t1, 40($sp)"); \
385  asm volatile("sw $t0, 36($sp)"); \
386  asm volatile("sw $a3, 32($sp)"); \
387  asm volatile("sw $a2, 28($sp)"); \
388  asm volatile("sw $a1, 24($sp)"); \
389  asm volatile("sw $a0, 20($sp)"); \
390  asm volatile("sw $v1, 16($sp)"); \
391  asm volatile("sw $v0, 12($sp)"); \
392  asm volatile("sw $at, 8($sp)"); \
393  asm volatile("mfhi $v0"); \
394  asm volatile("mflo $v1"); \
395  asm volatile("sw $v0, 4($sp)"); \
396  \
397  /* Call ISR */ \
398  asm volatile("la $t0, _func"#vec); \
399  asm volatile("jalr $t0"); \
400  asm volatile("sw $v1, 0($sp)"); \
401  \
402  /* Restore registers */ \
403  asm volatile("lw $v1, 0($sp)"); \
404  asm volatile("lw $v0, 4($sp)"); \
405  asm volatile("mtlo $v1"); \
406  asm volatile("mthi $v0"); \
407  asm volatile("lw $at, 8($sp)"); \
408  asm volatile("lw $v0, 12($sp)"); \
409  asm volatile("lw $v1, 16($sp)"); \
410  asm volatile("lw $a0, 20($sp)"); \
411  asm volatile("lw $a1, 24($sp)"); \
412  asm volatile("lw $a2, 28($sp)"); \
413  asm volatile("lw $a3, 32($sp)"); \
414  asm volatile("lw $t0, 36($sp)"); \
415  asm volatile("lw $t1, 40($sp)"); \
416  asm volatile("lw $t2, 44($sp)"); \
417  asm volatile("lw $t3, 48($sp)"); \
418  asm volatile("lw $t4, 52($sp)"); \
419  asm volatile("lw $t5, 56($sp)"); \
420  asm volatile("lw $t6, 60($sp)"); \
421  asm volatile("lw $t7, 64($sp)"); \
422  asm volatile("lw $t8, 68($sp)"); \
423  asm volatile("lw $t9, 72($sp)"); \
424  asm volatile("lw $ra, 76($sp)"); \
425  \
426  asm volatile("di"); \
427  asm volatile("ehb"); \
428  \
429  /* Restore context */ \
430  asm volatile("lw $k0, 84($sp)"); \
431  asm volatile("mtc0 $k0, $14"); /* c0_epc */ \
432  asm volatile("lw $k0, 80($sp)"); \
433  asm volatile("mtc0 $k0, $12, 2"); /* c0_srsctl */ \
434  asm volatile("addiu $sp, $sp, 92"); \
435  \
436  /* Decrease interrupt nesting count */ \
437  asm volatile("lui $k0, %hi(tn_p32_int_nest_count)"); \
438  asm volatile("lw $k1, %lo(tn_p32_int_nest_count)($k0)"); \
439  asm volatile("addiu $k1, $k1, -1"); \
440  asm volatile("sw $k1, %lo(tn_p32_int_nest_count)($k0)"); \
441  asm volatile("bne $k1, $zero, 1f"); \
442  asm volatile("lw $k1, -4($sp)"); \
443  \
444  /* Swap stack pointers if nesting count is zero */ \
445  asm volatile("lui $k0, %hi(tn_p32_int_sp)"); \
446  asm volatile("sw $sp, %lo(tn_p32_int_sp)($k0)"); \
447  asm volatile("lui $k0, %hi(tn_p32_user_sp)"); \
448  asm volatile("lw $sp, %lo(tn_p32_user_sp)($k0)"); \
449  \
450  asm volatile("1:"); \
451  asm volatile("wrpgpr $sp, $sp"); \
452  asm volatile("mtc0 $k1, $12"); /* c0_status */ \
453  asm volatile("eret"); \
454  \
455  asm volatile(".set pop"); \
456  \
457 } __attribute((__noinline__)) void _func##vec(void)
458 
459 
460 
461 
462 /**
463  * Interrupt handler wrapper macro for shadow register context saving.
464  *
465  * Usage looks like the following:
466  *
467  * tn_p32_srs_isr(_INT_UART_1_VECTOR)
468  * {
469  * INTClearFlag(INT_U1);
470  *
471  * //-- do something useful
472  * }
473  *
474  * Note that you should not use `__ISR(_INT_UART_1_VECTOR)` macro for that.
475  *
476  * @param vec interrupt vector number, such as `_TIMER_1_VECTOR`, etc.
477  */
478 #define tn_p32_srs_isr(vec) \
479 __attribute__((__noinline__)) void _func##vec(void); \
480 void __attribute__((naked, nomips16)) \
481  __attribute__((vector(vec))) \
482  _isr##vec(void) \
483 { \
484  asm volatile(".set push"); \
485  asm volatile(".set mips32r2"); \
486  asm volatile(".set nomips16"); \
487  asm volatile(".set noreorder"); \
488  asm volatile(".set noat"); \
489  \
490  asm volatile("rdpgpr $sp, $sp"); \
491  \
492  /* Increase interrupt nesting count */ \
493  asm volatile("lui $k0, %hi(tn_p32_int_nest_count)"); \
494  asm volatile("lw $k1, %lo(tn_p32_int_nest_count)($k0)"); \
495  asm volatile("addiu $k1, $k1, 1"); \
496  asm volatile("sw $k1, %lo(tn_p32_int_nest_count)($k0)"); \
497  asm volatile("ori $k0, $zero, 1"); \
498  asm volatile("bne $k1, $k0, 1f"); \
499  \
500  /* Swap stack pointers if nesting count is one */ \
501  asm volatile("lui $k0, %hi(tn_p32_user_sp)"); \
502  asm volatile("sw $sp, %lo(tn_p32_user_sp)($k0)"); \
503  asm volatile("lui $k0, %hi(tn_p32_int_sp)"); \
504  asm volatile("lw $sp, %lo(tn_p32_int_sp)($k0)"); \
505  \
506  asm volatile("1:"); \
507  /* Save context on stack */ \
508  asm volatile("addiu $sp, $sp, -20"); \
509  asm volatile("mfc0 $k1, $14"); /* c0_epc */ \
510  asm volatile("mfc0 $k0, $12, 2"); /* c0_srsctl */ \
511  asm volatile("sw $k1, 12($sp)"); \
512  asm volatile("sw $k0, 8($sp)"); \
513  asm volatile("mfc0 $k1, $12"); /* c0_status */ \
514  asm volatile("sw $k1, 16($sp)"); \
515  \
516  /* Enable nested interrupts */ \
517  asm volatile("mfc0 $k0, $13"); /* c0_cause */ \
518  asm volatile("ins $k1, $zero, 1, 15"); \
519  asm volatile("ext $k0, $k0, 10, 6"); \
520  asm volatile("ins $k1, $k0, 10, 6"); \
521  asm volatile("mtc0 $k1, $12"); /* c0_status */ \
522  \
523  /* Save caller-save registers on stack */ \
524  asm volatile("mfhi $v0"); \
525  asm volatile("mflo $v1"); \
526  asm volatile("sw $v0, 4($sp)"); \
527  \
528  /* Call ISR */ \
529  asm volatile("la $t0, _func"#vec); \
530  asm volatile("jalr $t0"); \
531  asm volatile("sw $v1, 0($sp)"); \
532  \
533  /* Restore registers */ \
534  asm volatile("lw $v1, 0($sp)"); \
535  asm volatile("lw $v0, 4($sp)"); \
536  asm volatile("mtlo $v1"); \
537  asm volatile("mthi $v0"); \
538  \
539  asm volatile("di"); \
540  asm volatile("ehb"); \
541  \
542  /* Restore context */ \
543  asm volatile("lw $k0, 12($sp)"); \
544  asm volatile("mtc0 $k0, $14"); /* c0_epc */ \
545  asm volatile("lw $k0, 8($sp)"); \
546  asm volatile("mtc0 $k0, $12, 2"); /* c0_srsctl */ \
547  asm volatile("addiu $sp, $sp, 20"); \
548  \
549  /* Decrease interrupt nesting count */ \
550  asm volatile("lui $k0, %hi(tn_p32_int_nest_count)"); \
551  asm volatile("lw $k1, %lo(tn_p32_int_nest_count)($k0)"); \
552  asm volatile("addiu $k1, $k1, -1"); \
553  asm volatile("sw $k1, %lo(tn_p32_int_nest_count)($k0)"); \
554  asm volatile("bne $k1, $zero, 1f"); \
555  asm volatile("lw $k1, -4($sp)"); \
556  \
557  /* Swap stack pointers if nesting count is zero */ \
558  asm volatile("lui $k0, %hi(tn_p32_int_sp)"); \
559  asm volatile("sw $sp, %lo(tn_p32_int_sp)($k0)"); \
560  asm volatile("lui $k0, %hi(tn_p32_user_sp)"); \
561  asm volatile("lw $sp, %lo(tn_p32_user_sp)($k0)"); \
562  \
563  asm volatile("1:"); \
564  asm volatile("wrpgpr $sp, $sp"); \
565  asm volatile("mtc0 $k1, $12"); /* c0_status */ \
566  asm volatile("eret"); \
567  \
568  asm volatile(".set pop"); \
569  \
570 } __attribute((__noinline__)) void _func##vec(void)
571 
572 
573 /**
574  * For compatibility with old projects, old name of `tn_p32_soft_isr()` macro
575  * is kept; please don't use it in new code.
576  */
577 #define tn_soft_isr tn_p32_soft_isr
578 
579 /**
580  * For compatibility with old projects, old name of `tn_p32_srs_isr()` macro
581  * is kept; please don't use it in new code.
582  */
583 #define tn_srs_isr tn_p32_srs_isr
584 
585 #ifdef __cplusplus
586 } /* extern "C" */
587 #endif
588 
589 #endif // _TN_ARCH_PIC32_H
590 
tn_p32_user_sp
void * tn_p32_user_sp
saved task stack pointer.
tn_p32_int_nest_count
volatile int tn_p32_int_nest_count
current interrupt nesting count.
tn_p32_int_sp
void * tn_p32_int_sp
saved ISR stack pointer.
TN_UIntPtr
unsigned int TN_UIntPtr
Unsigned integer type that is able to store pointers.
Definition: tn_arch_example.h:112
tn_arch_pic32_bfa.h
Atomic bit-field access macros for PIC24/dsPIC.
TN_UWord
unsigned int TN_UWord
Unsigned integer type whose size is equal to the size of CPU register.
Definition: tn_arch_example.h:105
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