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tn_arch_pic32.h
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1 /*******************************************************************************
2  *
3  * TNeoKernel: real-time kernel initially based on TNKernel
4  *
5  * TNKernel: copyright © 2004, 2013 Yuri Tiomkin.
6  * PIC32-specific routines: copyright © 2013, 2014 Anders Montonen.
7  * TNeoKernel: copyright © 2014 Dmitry Frank.
8  *
9  * TNeoKernel was born as a thorough review and re-implementation of
10  * TNKernel. The new kernel has well-formed code, inherited bugs are fixed
11  * as well as new features being added, and it is tested carefully with
12  * unit-tests.
13  *
14  * API is changed somewhat, so it's not 100% compatible with TNKernel,
15  * hence the new name: TNeoKernel.
16  *
17  * Permission to use, copy, modify, and distribute this software in source
18  * and binary forms and its documentation for any purpose and without fee
19  * is hereby granted, provided that the above copyright notice appear
20  * in all copies and that both that copyright notice and this permission
21  * notice appear in supporting documentation.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE DMITRY FRANK AND CONTRIBUTORS "AS IS"
24  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DMITRY FRANK OR CONTRIBUTORS BE
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30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33  * THE POSSIBILITY OF SUCH DAMAGE.
34  *
35  ******************************************************************************/
36 
37 /**
38  *
39  * \file
40  *
41  * PIC32 architecture-dependent routines
42  *
43  */
44 
45 #ifndef _TN_ARCH_PIC32_H
46 #define _TN_ARCH_PIC32_H
47 
48 //-- this include is needed to get build-time configuration
49 // (TN_DEBUG is used)
50 #include "../../core/tn_common.h"
51 
52 
53 #ifdef __cplusplus
54 extern "C" { /*}*/
55 #endif
56 
57 #ifndef DOXYGEN_SHOULD_SKIP_THIS
58 
59 #define _TN_PIC32_INTSAVE_DATA_INVALID 0xffffffff
60 
61 #if TN_DEBUG
62 # define _TN_PIC32_INTSAVE_CHECK() \
63 { \
64  if (tn_save_status_reg == _TN_PIC32_INTSAVE_DATA_INVALID){ \
65  _TN_FATAL_ERROR(""); \
66  } \
67 }
68 #else
69 # define _TN_PIC32_INTSAVE_CHECK() /* nothing */
70 #endif
71 
72 /**
73  * FFS - find first set bit. Used in `_find_next_task_to_run()` function.
74  * Say, for `0xa8` it should return `3`.
75  *
76  * May be not defined: in this case, naive algorithm will be used.
77  */
78 #define _TN_FFS(x) (32 - __builtin_clz((x) & (0 - (x))))
79 
80 /**
81  * Used by the kernel as a signal that something really bad happened.
82  * Indicates TNeoKernel bugs as well as illegal kernel usage
83  * (e.g. sleeping in the idle task callback)
84  *
85  * Typically, set to assembler instruction that causes debugger to halt.
86  */
87 #define _TN_FATAL_ERROR(error_msg, ...) \
88  {__asm__ volatile(" sdbbp 0"); __asm__ volatile ("nop");}
89 
90 
91 
92 /**
93  * \def TN_ARCH_STK_ATTR_BEFORE
94  *
95  * Compiler-specific attribute that should be placed **before** declaration of
96  * array used for stack. It is needed because there are often additional
97  * restrictions applied to alignment of stack, so, to meet them, stack arrays
98  * need to be declared with these macros.
99  *
100  * @see TN_ARCH_STK_ATTR_AFTER
101  */
102 
103 /**
104  * \def TN_ARCH_STK_ATTR_AFTER
105  *
106  * Compiler-specific attribute that should be placed **after** declaration of
107  * array used for stack. It is needed because there are often additional
108  * restrictions applied to alignment of stack, so, to meet them, stack arrays
109  * need to be declared with these macros.
110  *
111  * @see TN_ARCH_STK_ATTR_BEFORE
112  */
113 
114 #if defined (__XC32)
115 # define TN_ARCH_STK_ATTR_BEFORE
116 # define TN_ARCH_STK_ATTR_AFTER __attribute__((aligned(0x8)))
117 #else
118 # error "Unknown compiler"
119 #endif
120 
121 /**
122  * Minimum task's stack size, in words, not in bytes; includes a space for
123  * context plus for parameters passed to task's body function.
124  */
125 #define TN_MIN_STACK_SIZE 36
126 
127 /**
128  * Width of `int` type.
129  */
130 #define TN_INT_WIDTH 32
131 
132 /**
133  * Unsigned integer type whose size is equal to the size of CPU register.
134  * Typically it's plain `unsigned int`.
135  */
136 typedef unsigned int TN_UWord;
137 
138 
139 /**
140  * Maximum number of priorities available, this value usually matches
141  * `#TN_INT_WIDTH`.
142  *
143  * @see TN_PRIORITIES_CNT
144  */
145 #define TN_PRIORITIES_MAX_CNT TN_INT_WIDTH
146 
147 /**
148  * Value for infinite waiting, usually matches `UINT_MAX`
149  */
150 #define TN_WAIT_INFINITE 0xFFFFFFFF
151 
152 /**
153  * Value for initializing the task's stack
154  */
155 #define TN_FILL_STACK_VAL 0xFEEDFACE
156 
157 
158 
159 
160 /**
161  * Declares variable that is used by macros `TN_INT_DIS_SAVE()` and
162  * `TN_INT_RESTORE()` for storing status register value.
163  *
164  * It is good idea to initially set it to some invalid value,
165  * and if TN_DEBUG is non-zero, check it in TN_INT_RESTORE().
166  * Then, we can catch bugs if someone tries to restore interrupts status
167  * without saving it first.
168  *
169  * @see `TN_INT_DIS_SAVE()`
170  * @see `TN_INT_RESTORE()`
171  */
172 #define TN_INTSAVE_DATA \
173  int tn_save_status_reg = _TN_PIC32_INTSAVE_DATA_INVALID;
174 
175 /**
176  * The same as `#TN_INTSAVE_DATA` but for using in ISR together with
177  * `TN_INT_IDIS_SAVE()`, `TN_INT_IRESTORE()`.
178  *
179  * @see `TN_INT_IDIS_SAVE()`
180  * @see `TN_INT_IRESTORE()`
181  */
182 #define TN_INTSAVE_DATA_INT TN_INTSAVE_DATA
183 
184 /**
185  * \def TN_INT_DIS_SAVE()
186  *
187  * Disable interrupts and return previous value of status register,
188  * atomically. Similar `tn_arch_sr_save_int_dis()`, but implemented
189  * as a macro, so it is potentially faster.
190  *
191  * Uses `#TN_INTSAVE_DATA` as a temporary storage.
192  *
193  * @see `#TN_INTSAVE_DATA`
194  * @see `tn_arch_sr_save_int_dis()`
195  */
196 
197 /**
198  * \def TN_INT_RESTORE()
199  *
200  * Restore previously saved status register.
201  * Similar to `tn_arch_sr_restore()`, but implemented as a macro,
202  * so it is potentially faster.
203  *
204  * Uses `#TN_INTSAVE_DATA` as a temporary storage.
205  *
206  * @see `#TN_INTSAVE_DATA`
207  * @see `tn_arch_sr_save_int_dis()`
208  */
209 
210 #ifdef __mips16
211 # define TN_INT_DIS_SAVE() tn_save_status_reg = tn_arch_sr_save_int_dis()
212 # define TN_INT_RESTORE() _TN_PIC32_INTSAVE_CHECK(); \
213  tn_arch_sr_restore(tn_save_status_reg)
214 #else
215 # define TN_INT_DIS_SAVE() __asm__ __volatile__( \
216  "di %0; ehb" \
217  : "=d" (tn_save_status_reg) \
218  )
219 # define TN_INT_RESTORE() _TN_PIC32_INTSAVE_CHECK(); \
220  __builtin_mtc0(12, 0, tn_save_status_reg)
221 #endif
222 
223 /**
224  * The same as `TN_INT_DIS_SAVE()` but for using in ISR.
225  *
226  * Uses `#TN_INTSAVE_DATA_INT` as a temporary storage.
227  *
228  * @see `#TN_INTSAVE_DATA_INT`
229  */
230 #define TN_INT_IDIS_SAVE() TN_INT_DIS_SAVE()
231 
232 /**
233  * The same as `TN_INT_RESTORE()` but for using in ISR.
234  *
235  * Uses `#TN_INTSAVE_DATA_INT` as a temporary storage.
236  *
237  * @see `#TN_INTSAVE_DATA_INT`
238  */
239 #define TN_INT_IRESTORE() TN_INT_RESTORE()
240 
241 /**
242  * Returns nonzero if interrupts are disabled, zero otherwise.
243  */
244 #define TN_IS_INT_DISABLED() ((__builtin_mfc0(12, 0) & 1) == 0)
245 
246 /**
247  * Pend context switch from interrupt.
248  */
249 #define _TN_CONTEXT_SWITCH_IPEND_IF_NEEDED() \
250  _tn_context_switch_pend_if_needed()
251 
252 
253 
254 #endif //-- DOXYGEN_SHOULD_SKIP_THIS
255 
256 
257 
258 
259 
260 
261 
262 
263 
264 
265 // ---------------------------------------------------------------------------
266 
267 /**
268  * Interrupt handler wrapper macro for software context saving.
269  *
270  * Usage looks like the following:
271  *
272  * tn_soft_isr(_TIMER_1_VECTOR)
273  * {
274  * INTClearFlag(INT_T1);
275  *
276  * //-- do something useful
277  * }
278  *
279  * Note that you should not use `__ISR(_TIMER_1_VECTOR)` macro for that.
280  *
281  * @param vec interrupt vector number, such as `_TIMER_1_VECTOR`, etc.
282  */
283 #define tn_soft_isr(vec) \
284 __attribute__((__noinline__)) void _func##vec(void); \
285 void __attribute__((naked, nomips16)) \
286  __attribute__((vector(vec))) \
287  _isr##vec(void) \
288 { \
289  asm volatile(".set push"); \
290  asm volatile(".set mips32r2"); \
291  asm volatile(".set nomips16"); \
292  asm volatile(".set noreorder"); \
293  asm volatile(".set noat"); \
294  \
295  asm volatile("rdpgpr $sp, $sp"); \
296  \
297  /* Increase interrupt nesting count */ \
298  asm volatile("lui $k0, %hi(tn_int_nest_count)"); \
299  asm volatile("lw $k1, %lo(tn_int_nest_count)($k0)"); \
300  asm volatile("addiu $k1, $k1, 1"); \
301  asm volatile("sw $k1, %lo(tn_int_nest_count)($k0)"); \
302  asm volatile("ori $k0, $zero, 1"); \
303  asm volatile("bne $k1, $k0, 1f"); \
304  \
305  /* Swap stack pointers if nesting count is one */ \
306  asm volatile("lui $k0, %hi(tn_user_sp)"); \
307  asm volatile("sw $sp, %lo(tn_user_sp)($k0)"); \
308  asm volatile("lui $k0, %hi(tn_int_sp)"); \
309  asm volatile("lw $sp, %lo(tn_int_sp)($k0)"); \
310  \
311  asm volatile("1:"); \
312  /* Save context on stack */ \
313  asm volatile("addiu $sp, $sp, -92"); \
314  asm volatile("mfc0 $k1, $14"); /* c0_epc*/ \
315  asm volatile("mfc0 $k0, $12, 2"); /* c0_srsctl*/ \
316  asm volatile("sw $k1, 84($sp)"); \
317  asm volatile("sw $k0, 80($sp)"); \
318  asm volatile("mfc0 $k1, $12"); /* c0_status*/ \
319  asm volatile("sw $k1, 88($sp)"); \
320  \
321  /* Enable nested interrupts */ \
322  asm volatile("mfc0 $k0, $13"); /* c0_cause*/ \
323  asm volatile("ins $k1, $zero, 1, 15"); \
324  asm volatile("ext $k0, $k0, 10, 6"); \
325  asm volatile("ins $k1, $k0, 10, 6"); \
326  asm volatile("mtc0 $k1, $12"); /* c0_status*/ \
327  \
328  /* Save caller-save registers on stack */ \
329  asm volatile("sw $ra, 76($sp)"); \
330  asm volatile("sw $t9, 72($sp)"); \
331  asm volatile("sw $t8, 68($sp)"); \
332  asm volatile("sw $t7, 64($sp)"); \
333  asm volatile("sw $t6, 60($sp)"); \
334  asm volatile("sw $t5, 56($sp)"); \
335  asm volatile("sw $t4, 52($sp)"); \
336  asm volatile("sw $t3, 48($sp)"); \
337  asm volatile("sw $t2, 44($sp)"); \
338  asm volatile("sw $t1, 40($sp)"); \
339  asm volatile("sw $t0, 36($sp)"); \
340  asm volatile("sw $a3, 32($sp)"); \
341  asm volatile("sw $a2, 28($sp)"); \
342  asm volatile("sw $a1, 24($sp)"); \
343  asm volatile("sw $a0, 20($sp)"); \
344  asm volatile("sw $v1, 16($sp)"); \
345  asm volatile("sw $v0, 12($sp)"); \
346  asm volatile("sw $at, 8($sp)"); \
347  asm volatile("mfhi $v0"); \
348  asm volatile("mflo $v1"); \
349  asm volatile("sw $v0, 4($sp)"); \
350  \
351  /* Call ISR */ \
352  asm volatile("la $t0, _func"#vec); \
353  asm volatile("jalr $t0"); \
354  asm volatile("sw $v1, 0($sp)"); \
355  \
356  /* Restore registers */ \
357  asm volatile("lw $v1, 0($sp)"); \
358  asm volatile("lw $v0, 4($sp)"); \
359  asm volatile("mtlo $v1"); \
360  asm volatile("mthi $v0"); \
361  asm volatile("lw $at, 8($sp)"); \
362  asm volatile("lw $v0, 12($sp)"); \
363  asm volatile("lw $v1, 16($sp)"); \
364  asm volatile("lw $a0, 20($sp)"); \
365  asm volatile("lw $a1, 24($sp)"); \
366  asm volatile("lw $a2, 28($sp)"); \
367  asm volatile("lw $a3, 32($sp)"); \
368  asm volatile("lw $t0, 36($sp)"); \
369  asm volatile("lw $t1, 40($sp)"); \
370  asm volatile("lw $t2, 44($sp)"); \
371  asm volatile("lw $t3, 48($sp)"); \
372  asm volatile("lw $t4, 52($sp)"); \
373  asm volatile("lw $t5, 56($sp)"); \
374  asm volatile("lw $t6, 60($sp)"); \
375  asm volatile("lw $t7, 64($sp)"); \
376  asm volatile("lw $t8, 68($sp)"); \
377  asm volatile("lw $t9, 72($sp)"); \
378  asm volatile("lw $ra, 76($sp)"); \
379  \
380  asm volatile("di"); \
381  asm volatile("ehb"); \
382  \
383  /* Restore context */ \
384  asm volatile("lw $k0, 84($sp)"); \
385  asm volatile("mtc0 $k0, $14"); /* c0_epc */ \
386  asm volatile("lw $k0, 80($sp)"); \
387  asm volatile("mtc0 $k0, $12, 2"); /* c0_srsctl */ \
388  asm volatile("addiu $sp, $sp, 92"); \
389  \
390  /* Decrease interrupt nesting count */ \
391  asm volatile("lui $k0, %hi(tn_int_nest_count)"); \
392  asm volatile("lw $k1, %lo(tn_int_nest_count)($k0)"); \
393  asm volatile("addiu $k1, $k1, -1"); \
394  asm volatile("sw $k1, %lo(tn_int_nest_count)($k0)"); \
395  asm volatile("bne $k1, $zero, 1f"); \
396  asm volatile("lw $k1, -4($sp)"); \
397  \
398  /* Swap stack pointers if nesting count is zero */ \
399  asm volatile("lui $k0, %hi(tn_int_sp)"); \
400  asm volatile("sw $sp, %lo(tn_int_sp)($k0)"); \
401  asm volatile("lui $k0, %hi(tn_user_sp)"); \
402  asm volatile("lw $sp, %lo(tn_user_sp)($k0)"); \
403  \
404  asm volatile("1:"); \
405  asm volatile("wrpgpr $sp, $sp"); \
406  asm volatile("mtc0 $k1, $12"); /* c0_status */ \
407  asm volatile("eret"); \
408  \
409  asm volatile(".set pop"); \
410  \
411 } __attribute((__noinline__)) void _func##vec(void)
412 
413 
414 
415 
416 /**
417  * Interrupt handler wrapper macro for shadow register context saving.
418  *
419  * Usage looks like the following:
420  *
421  * tn_srs_isr(_INT_UART_1_VECTOR)
422  * {
423  * INTClearFlag(INT_U1);
424  *
425  * //-- do something useful
426  * }
427  *
428  * Note that you should not use `__ISR(_INT_UART_1_VECTOR)` macro for that.
429  *
430  * @param vec interrupt vector number, such as `_TIMER_1_VECTOR`, etc.
431  */
432 #define tn_srs_isr(vec) \
433 __attribute__((__noinline__)) void _func##vec(void); \
434 void __attribute__((naked, nomips16)) \
435  __attribute__((vector(vec))) \
436  _isr##vec(void) \
437 { \
438  asm volatile(".set push"); \
439  asm volatile(".set mips32r2"); \
440  asm volatile(".set nomips16"); \
441  asm volatile(".set noreorder"); \
442  asm volatile(".set noat"); \
443  \
444  asm volatile("rdpgpr $sp, $sp"); \
445  \
446  /* Increase interrupt nesting count */ \
447  asm volatile("lui $k0, %hi(tn_int_nest_count)"); \
448  asm volatile("lw $k1, %lo(tn_int_nest_count)($k0)"); \
449  asm volatile("addiu $k1, $k1, 1"); \
450  asm volatile("sw $k1, %lo(tn_int_nest_count)($k0)"); \
451  asm volatile("ori $k0, $zero, 1"); \
452  asm volatile("bne $k1, $k0, 1f"); \
453  \
454  /* Swap stack pointers if nesting count is one */ \
455  asm volatile("lui $k0, %hi(tn_user_sp)"); \
456  asm volatile("sw $sp, %lo(tn_user_sp)($k0)"); \
457  asm volatile("lui $k0, %hi(tn_int_sp)"); \
458  asm volatile("lw $sp, %lo(tn_int_sp)($k0)"); \
459  \
460  asm volatile("1:"); \
461  /* Save context on stack */ \
462  asm volatile("addiu $sp, $sp, -20"); \
463  asm volatile("mfc0 $k1, $14"); /* c0_epc */ \
464  asm volatile("mfc0 $k0, $12, 2"); /* c0_srsctl */ \
465  asm volatile("sw $k1, 12($sp)"); \
466  asm volatile("sw $k0, 8($sp)"); \
467  asm volatile("mfc0 $k1, $12"); /* c0_status */ \
468  asm volatile("sw $k1, 16($sp)"); \
469  \
470  /* Enable nested interrupts */ \
471  asm volatile("mfc0 $k0, $13"); /* c0_cause */ \
472  asm volatile("ins $k1, $zero, 1, 15"); \
473  asm volatile("ext $k0, $k0, 10, 6"); \
474  asm volatile("ins $k1, $k0, 10, 6"); \
475  asm volatile("mtc0 $k1, $12"); /* c0_status */ \
476  \
477  /* Save caller-save registers on stack */ \
478  asm volatile("mfhi $v0"); \
479  asm volatile("mflo $v1"); \
480  asm volatile("sw $v0, 4($sp)"); \
481  \
482  /* Call ISR */ \
483  asm volatile("la $t0, _func"#vec); \
484  asm volatile("jalr $t0"); \
485  asm volatile("sw $v1, 0($sp)"); \
486  \
487  /* Restore registers */ \
488  asm volatile("lw $v1, 0($sp)"); \
489  asm volatile("lw $v0, 4($sp)"); \
490  asm volatile("mtlo $v1"); \
491  asm volatile("mthi $v0"); \
492  \
493  asm volatile("di"); \
494  asm volatile("ehb"); \
495  \
496  /* Restore context */ \
497  asm volatile("lw $k0, 12($sp)"); \
498  asm volatile("mtc0 $k0, $14"); /* c0_epc */ \
499  asm volatile("lw $k0, 8($sp)"); \
500  asm volatile("mtc0 $k0, $12, 2"); /* c0_srsctl */ \
501  asm volatile("addiu $sp, $sp, 20"); \
502  \
503  /* Decrease interrupt nesting count */ \
504  asm volatile("lui $k0, %hi(tn_int_nest_count)"); \
505  asm volatile("lw $k1, %lo(tn_int_nest_count)($k0)"); \
506  asm volatile("addiu $k1, $k1, -1"); \
507  asm volatile("sw $k1, %lo(tn_int_nest_count)($k0)"); \
508  asm volatile("bne $k1, $zero, 1f"); \
509  asm volatile("lw $k1, -4($sp)"); \
510  \
511  /* Swap stack pointers if nesting count is zero */ \
512  asm volatile("lui $k0, %hi(tn_int_sp)"); \
513  asm volatile("sw $sp, %lo(tn_int_sp)($k0)"); \
514  asm volatile("lui $k0, %hi(tn_user_sp)"); \
515  asm volatile("lw $sp, %lo(tn_user_sp)($k0)"); \
516  \
517  asm volatile("1:"); \
518  asm volatile("wrpgpr $sp, $sp"); \
519  asm volatile("mtc0 $k1, $12"); /* c0_status */ \
520  asm volatile("eret"); \
521  \
522  asm volatile(".set pop"); \
523  \
524 } __attribute((__noinline__)) void _func##vec(void)
525 
526 
527 #ifdef __cplusplus
528 } /* extern "C" */
529 #endif
530 
531 #endif // _TN_ARCH_PIC32_H
532 
TN_UWord
unsigned int TN_UWord
Unsigned integer type whose size is equal to the size of CPU register.
Definition: tn_arch_example.h:104
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